A 0.13 μm low-power race-free programmable logic array

Giby Samson

doi:10.1109/CICC.2006.320899

A 0.13 μm low-power race-free programmable logic array

Giby Samson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at V_DD = 1.5 V.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages	313-316
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2006.320899
State	Published - 2006
Event	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States Duration: Sep 10 2006 → Sep 13 2006

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference

Other

Other	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/Territory	United States
City	San Jose, CA
Period	9/10/06 → 9/13/06

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2006.320899

Cite this

Samson, G 2006, A 0.13 μm low-power race-free programmable logic array. in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006., 4114967, Proceedings of the Custom Integrated Circuits Conference, pp. 313-316, IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, San Jose, CA, United States, 9/10/06. https://doi.org/10.1109/CICC.2006.320899

@inproceedings{9d91be83c42741bca06b54c8c341bf39,

title = "A 0.13 μm low-power race-free programmable logic array",

abstract = "A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50\% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10\% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.",

author = "Giby Samson",

year = "2006",

doi = "10.1109/CICC.2006.320899",

language = "English (US)",

isbn = "1424400767",

series = "Proceedings of the Custom Integrated Circuits Conference",

pages = "313--316",

booktitle = "Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006",

note = "IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 ; Conference date: 10-09-2006 Through 13-09-2006",

}

TY - GEN

T1 - A 0.13 μm low-power race-free programmable logic array

AU - Samson, Giby

PY - 2006

Y1 - 2006

N2 - A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.

AB - A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.

UR - https://www.scopus.com/pages/publications/39049095143

UR - https://www.scopus.com/pages/publications/39049095143#tab=citedBy

U2 - 10.1109/CICC.2006.320899

DO - 10.1109/CICC.2006.320899

M3 - Conference contribution

SN - 1424400767

SN - 9781424400768

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 313

EP - 316

BT - Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006

T2 - IEEE 2006 Custom Integrated Circuits Conference, CICC 2006

Y2 - 10 September 2006 through 13 September 2006

ER -

A 0.13 μm low-power race-free programmable logic array

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this