A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

Jongeun Lee; Aviral Shrivastava

doi:10.1109/TCAD.2010.2049050

A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

Jongeun Lee
, Aviral Shrivastava

Research output: Contribution to journal › Article › peer-review

20 Scopus citations

Abstract

For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.

Original language	English (US)
Pages (from-to)	1018-1027
Number of pages	10
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	29
Issue number	7
DOIs	https://doi.org/10.1109/TCAD.2010.2049050
State	Published - Jul 2010

Keywords

Compiler-architecture hybrid
embedded processor design
energy
partially protected register file (PPRF)
register file vulnerability (RFV)
reliability

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2010.2049050

Cite this

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title = "A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files",

abstract = "For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30\% on average, as demonstrated in our experiments on a number of embedded application benchmarks.",

keywords = "Compiler-architecture hybrid, embedded processor design, energy, partially protected register file (PPRF), register file vulnerability (RFV), reliability",

author = "Jongeun Lee and Aviral Shrivastava",

note = "Funding Information: Manuscript received March 7, 2009; revised November 10, 2009. Date of current version June 18, 2010. This research was partially funded by the National Science Foundation (NSF), under Grants CCF-0916652, IIP-0856090, and NSF I/UCRC for Embedded Systems, by Microsoft Research, by Raytheon, by the SFAz, by the Stardust Foundation, and by the Basic Science Research Program through the National Research Foundation of Korea (funded by MEST), under Grant 2010-0011534. The authors would like to thank all the members of the Compiler Microarchitecture Laboratory for their valuable support in this paper. This paper was recommended by Associate Editor S. A. Edwards.",

year = "2010",

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doi = "10.1109/TCAD.2010.2049050",

language = "English (US)",

volume = "29",

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AU - Lee, Jongeun

AU - Shrivastava, Aviral

N1 - Funding Information: Manuscript received March 7, 2009; revised November 10, 2009. Date of current version June 18, 2010. This research was partially funded by the National Science Foundation (NSF), under Grants CCF-0916652, IIP-0856090, and NSF I/UCRC for Embedded Systems, by Microsoft Research, by Raytheon, by the SFAz, by the Stardust Foundation, and by the Basic Science Research Program through the National Research Foundation of Korea (funded by MEST), under Grant 2010-0011534. The authors would like to thank all the members of the Compiler Microarchitecture Laboratory for their valuable support in this paper. This paper was recommended by Associate Editor S. A. Edwards.

PY - 2010/7

Y1 - 2010/7

N2 - For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.

AB - For embedded systems, where neither energy nor reliability can be easily sacrificed, this paper presents an energy efficient soft error protection scheme for register files (RFs). Unlike previous approaches, the proposed method explicitly optimizes for energy efficiency and can exploit the fundamental tradeoff between reliability and energy. While even simple compiler-managed RF protection scheme can be more energy efficient than hardware schemes, this paper formulates and solves further compiler optimization problems to significantly enhance the energy efficiency of RF protection schemes by an additional 30% on average, as demonstrated in our experiments on a number of embedded application benchmarks.

KW - Compiler-architecture hybrid

KW - embedded processor design

KW - energy

KW - partially protected register file (PPRF)

KW - register file vulnerability (RFV)

KW - reliability

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UR - https://www.scopus.com/pages/publications/85008014183#tab=citedBy

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JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files

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Keywords

ASJC Scopus subject areas

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