@inproceedings{6cee6091b04546329c02f533b4a5c806,
title = "A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs",
abstract = "Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFTRT) on the FPGA. We conduct performance evaluations on an SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFTRT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183 based on workloads composed of a mixture of dynamically ×arriving real-life signal processing applications.",
keywords = "FPGA, Scheduling, hardware emulation, multiprocessor SoC, system on chip",
author = "Alexander Fusco and Sahil Hassan and Joshua Mack and Ali Akoglu",
note = "Funding Information: This material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650-18-2-7860. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusion contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of Air Force Research Laboratory (AFRL) and Defence Advanced Research Projects Agency (DARPA) or the U.S. Government. Publisher Copyright: {\textcopyright} 2022 IEEE.; 30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022 ; Conference date: 01-01-2022",
year = "2022",
doi = "https://doi.org/10.1109/VLSI-SoC54400.2022.9939623",
language = "English (US)",
series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",
publisher = "IEEE Computer Society",
booktitle = "Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022",
}