TY - JOUR
T1 - A run-time verification method with consideration of uncertainties for cyber–physical systems
AU - Mehrabian, Mohammadreza
AU - Khayatian, Mohammad
AU - Shrivastava, Aviral
AU - Derler, Patricia
AU - Andrade, Hugo
N1 - Funding Information: Aviral Shrivastava is a full Professor in the School of Computing and Augmented Intelligence (SCAI) at the Arizona State University, where he established and heads the Make Programming Simple Lab ( https://labs.engineering.asu.edu/mps-lab/ ). He completed his Ph.D. in Information and Computer Science and from the University of California, Irvine, and Bachelors in Computer Science and Engineering from IIT Delhi. Prof. Shrivastava’s main theme of research in on making programming simple for embedded and cyber–physical systems. Prof. Shrivastava and his students have proposed novel computer architectures and compiler transformations for hardware errortolerant computing, multicore computing, accelerated computing. They have also proposed languages, code generation and runtime for expressing and efficiently executing time-sensitive distributed intelligent applications. Prof. Shrivastava has co-authored 1 book, and has contributed chapters in 4 books. He has more than 120 articles and conference papers in top embedded system journals and conferences, like DAC, ESWEEK, ACM TECS, and ACM TCPS. His papers have received several awards, including nomination for best paper at DAC 2017, best student paper award at VLSI 2016, second highest ranked paper at LCTES 2010, and best paper candidate ASPDAC 2008. He published at least one paper every year at DAC (the top conference in the field) in the last decade (2011 to 2019). Overall, his works have received more than 3000 citations, growing at the rate of over 200 citations every year. His i50-index is 14, i10-index is 84, and hindex is 31 (reference Google Scholar). His inventions have been granted 5 patents, and 5 more applications are pending. Prof. Shrivastava is the recipient of the prestigious 2010 NSF CAREER award. His students thesis were awarded CIDSE outstanding Ph.D. thesis award in 2021 and 2017 and outstanding Master’s thesis awards in 2011 and 2014. Prof. Shrivastava’s research efforts have been supported by federal agencies (NSF, DOE, NIST), state funding agencies (SFAZ), as well as industry. Prof. Shrivastava has mentored 2 postdocs, 9 Ph.D. students, and over 20 Masters students. His students are very well placed, including a full Professor at UNIST, South Korea, Assistant Professor at SJSU, ARM research lab, Google, Synopsys, Apple (x2), Qualcomm, Cadence etc. Prof. Shrivastava is currently supervising 3 Ph.D., and 5 Masters students. Prof. Shrivastava teaches undergraduate and graduate level courses on computer organization, computer architecture, and embedded systems, and has student evaluations averaging over 4/5. He revamped the computer organization and computer Architecture courses at ASU to shift the focus towards processor design instead of assembly language programming and included modules about modern multicore architectures. He has redesigned the embedded systems course around projects in which students build an autonomously driving car, culminating in an autonomous car race! ( https://www.youtube.com/channel/UCDfyzk7HFqeXCb5BK02SemQ )Prof. Shrivastava is currently the General Chair of Embedded Systems Week (ESWEEK), which is the top event in the field of Embedded Systems, comprising of several conferences, symposia and workshops. He also serves in the Steering committee of the Languages Compilers, Theory and tools for Embedded Systems (LCTES). Currently, he is the deputy Editor-in-Chief of IEEE Embedded Systems Letters (IEEE ESL), and associate editor for ACM Transactions of Cyber-Physical Systems (ACM TCPS), ACM Transactions Embedded Computing Systems (ACM TECS), and the IEEE Transactions on Computer Aided Design (IEEE TCAD). Previously he has served as the program chair of CODES+ISSS 2017 and 2018, LCTES 2019, and chair of the Design and Applications track of RTSS 2020. Publisher Copyright: © 2023 Elsevier B.V.
PY - 2023/9
Y1 - 2023/9
N2 - Since many Cyber–Physical Systems (CPS) interact with the real world, they are safety- or mission- critical. Temporal specification languages like STL (Signal Temporal Logic) have been developed to capture the properties that built CPS must meet. However, the existing temporal logics/languages do not provide a natural way to express the tolerance with which the timing properties must be met. As a consequence of this, the specified properties may be vague, the ensuing CPS design may end up being over- or under-provisioned, and the validation of whether the built CPS meets the specified CPS properties may turn out to be erroneous. To address these issues, a run-time verification methodology is proposed, that allows users to explicitly specify the tolerance with which timing properties must be met. To ensure the correctness of measurement-based validation of a built CPS, this article: (i) proposes a test to determine if a given measurement system can validate the properties specified in TTL, and (ii) proposes a measurement-based testing methodology to provide one-sided guarantee that the built CPS meets the specified CPS properties. The guarantees are one-sided in the sense that when the measurement-based testing concludes that the properties are met, then they are guaranteed to be met (so not false positive). However, when the measurement-based testing concludes that the properties were not met, then they may have met (there can be false negative). In order to validate our claims, we built a model of flying paster (part of the printing press that swaps in a new roll of paper when the current roll is about to finish) using Arduino Mega 2560 and two Hansen brushed DC motors and specified the timing constraints among the various events in this system, along with the tolerances with which they should be met in TTL. We generated the testing logic and validated that we get no false positive, even though we encounter 4.04% false negative. The rate of false negatives can be reduced to be less than any arbitrary value by using more accurate measurement equipment.
AB - Since many Cyber–Physical Systems (CPS) interact with the real world, they are safety- or mission- critical. Temporal specification languages like STL (Signal Temporal Logic) have been developed to capture the properties that built CPS must meet. However, the existing temporal logics/languages do not provide a natural way to express the tolerance with which the timing properties must be met. As a consequence of this, the specified properties may be vague, the ensuing CPS design may end up being over- or under-provisioned, and the validation of whether the built CPS meets the specified CPS properties may turn out to be erroneous. To address these issues, a run-time verification methodology is proposed, that allows users to explicitly specify the tolerance with which timing properties must be met. To ensure the correctness of measurement-based validation of a built CPS, this article: (i) proposes a test to determine if a given measurement system can validate the properties specified in TTL, and (ii) proposes a measurement-based testing methodology to provide one-sided guarantee that the built CPS meets the specified CPS properties. The guarantees are one-sided in the sense that when the measurement-based testing concludes that the properties are met, then they are guaranteed to be met (so not false positive). However, when the measurement-based testing concludes that the properties were not met, then they may have met (there can be false negative). In order to validate our claims, we built a model of flying paster (part of the printing press that swaps in a new roll of paper when the current roll is about to finish) using Arduino Mega 2560 and two Hansen brushed DC motors and specified the timing constraints among the various events in this system, along with the tolerances with which they should be met in TTL. We generated the testing logic and validated that we get no false positive, even though we encounter 4.04% false negative. The rate of false negatives can be reduced to be less than any arbitrary value by using more accurate measurement equipment.
KW - Cyber–physical systems
KW - IoT
KW - Real-time systems
KW - Robotics
KW - Run-time verification
KW - Temporal logic
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U2 - 10.1016/j.micpro.2023.104890
DO - 10.1016/j.micpro.2023.104890
M3 - Article
SN - 0141-9331
VL - 101
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
M1 - 104890
ER -