TY - GEN
T1 - A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation
AU - Kuan, Kyle
AU - Adegbija, Tosiron
N1 - Funding Information: ACKNOWLEDGEMENT This work was supported by the National Science Foundation (NSF) under grant CNS-1844952. Any opinions, findings, conclusions, or recommendations expressed are those of the authors and do not necessarily reflect the views of the NSF. Publisher Copyright: © 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper studies spin-transfer torque RAM (STTRAM) as an energy-efficient alternative to SRAM for implementing page walker caches (PWCs) in resource-constrained systems' memory management units. We analyze the access characteristics and persistence of PWC blocks in a set of multithreaded workloads, revealing that individual threads might have different runtime behaviors. Given this observation, we explore and analyze the benefits of heterogeneous retention time STTRAM-wherein STTRAM's data retention time is specialized to cache blocks' persistence needs-for implementing the PWC in multicore systems. Based on our analysis, we propose NECTAR, an energy-efficient heterogeneous STTRAM-based page walker cache architecture. Experimental results using multithreaded PARSEC benchmarks show that NECTAR enables runtime adaptability and offers substantial energy benefits for implementing the PWC, reducing the average energy by 81.36% compared to SRAM, without introducing significant overheads.
AB - This paper studies spin-transfer torque RAM (STTRAM) as an energy-efficient alternative to SRAM for implementing page walker caches (PWCs) in resource-constrained systems' memory management units. We analyze the access characteristics and persistence of PWC blocks in a set of multithreaded workloads, revealing that individual threads might have different runtime behaviors. Given this observation, we explore and analyze the benefits of heterogeneous retention time STTRAM-wherein STTRAM's data retention time is specialized to cache blocks' persistence needs-for implementing the PWC in multicore systems. Based on our analysis, we propose NECTAR, an energy-efficient heterogeneous STTRAM-based page walker cache architecture. Experimental results using multithreaded PARSEC benchmarks show that NECTAR enables runtime adaptability and offers substantial energy benefits for implementing the PWC, reducing the average energy by 81.36% compared to SRAM, without introducing significant overheads.
KW - energy-efficient address translation
KW - Page walker cache
KW - spin-transfer torque RAM cache
UR - http://www.scopus.com/inward/record.url?scp=85140894697&partnerID=8YFLogxK
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U2 - https://doi.org/10.1109/ISVLSI54635.2022.00026
DO - https://doi.org/10.1109/ISVLSI54635.2022.00026
M3 - Conference contribution
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 74
EP - 79
BT - Proceedings - 2022 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022
PB - IEEE Computer Society
T2 - 2022 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022
Y2 - 1 January 2022
ER -