ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Computer Science

• Convolutional Neural Network 100%
• Deep Learning 100%
• Design Strategy 25%
• hardware acceleration 25%
• Hardware Level 25%
• High Level Synthesis 50%
• Inference Task 25%
• Memory Access 25%
• Neural Network Model 50%
• OpenCL 50%
• Parallelism 25%
• Resource Allocation 25%
• Resource Constraint 25%
• Synthesis Tool 25%
• System Architectures 25%

Keyphrases

• End-to-end Convolutional Neural Network 50%
• Great Acceleration 50%
• Hardware Acceleration of Deep Learning 50%
• High-level Synthesis Tools 50%
• OpenCL for FPGA 50%
• RTL Implementation 50%