TY - GEN
T1 - An efficient combinationality check technique for the synthesis of cyclic combinational circuits
AU - Agarwal, Vineet
AU - Kankani, Navneeth
AU - Rao, Ravishankar
AU - Bhardwaj, Sarvesh
AU - Wang, Janet
PY - 2005
Y1 - 2005
N2 - It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45% improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.
AB - It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45% improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.
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U2 - 10.1145/1120725.1120807
DO - 10.1145/1120725.1120807
M3 - Conference contribution
SN - 0780387368
SN - 9780780387362
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 212
EP - 215
BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Y2 - 18 January 2005 through 21 January 2005
ER -