TY - JOUR
T1 - An embeddable multilevel-cell solid electrolyte memory array
AU - Gilbert, Nad E.
AU - Kozicki, Michael
N1 - Funding Information: Manuscript received August 31, 2006; revised January 8, 2007. This work was supported by Axon Technologies Corporation. N. E. Gilbert is with Desert Microtechnology Associates Inc., Scottsdale, AZ 85260 USA. M. N. Kozicki is with the Center for Applied Nanoionics, Arizona State University, Tempe, AZ 85287-6206 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2007.897172
PY - 2007/6
Y1 - 2007/6
N2 - Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-current operation and a simple process that allows them to be integrated with conventional CMOS processes with minimal additional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The compact memory design addresses many of the unusual operational issues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18-μm CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10-μA reference current with a 437-ns cycle time and sub-40-ns access times.
AB - Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-current operation and a simple process that allows them to be integrated with conventional CMOS processes with minimal additional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The compact memory design addresses many of the unusual operational issues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18-μm CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10-μA reference current with a 437-ns cycle time and sub-40-ns access times.
KW - Multilevel cell (MLC)
KW - Nonvolatile memory
KW - Programmable metallization cell
KW - Solid electrolyte
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U2 - 10.1109/JSSC.2007.897172
DO - 10.1109/JSSC.2007.897172
M3 - Article
SN - 0018-9200
VL - 42
SP - 1383
EP - 1391
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -