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Automated Hardware Logic Obfuscation Framework Using GPT

  • Banafsheh Saber Latibari
  • , Sujan Ghimire
  • , Muhtasim Alam Chowdhury
  • , Najmeh Nazari
  • , Kevin Immanuel Gubbi
  • , Houman Homayoun
  • , Avesta Sasan
  • , Soheil Salehi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Obfuscation stands as a promising solution for safe-guarding hardware intellectual property (IP) against a spectrum of threats including reverse engineering, IP piracy, and tampering. In this paper, we introduce Obfus-chat, a novel framework leveraging Generative Pre-trained Transformer (GPT) models to automate the obfuscation process. The proposed framework accepts hardware design netlists and key sizes as inputs, and autonomously generates obfuscated code tailored to enhance security. To evaluate the effectiveness of our approach, we employ the Trust-Hub Obfuscation Benchmark for comparative analysis. We employed SAT attacks to assess the security of the design, along with functional verification procedures to ensure that the obfuscated design remains consistent with the original. Our results demonstrate the efficacy and efficiency of the proposed framework in fortifying hardware IP against potential threats, thus providing a valuable contribution to the field of hardware security.

Original languageEnglish (US)
Title of host publicationProceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350349535
DOIs
StatePublished - 2024
Event17th IEEE Dallas Circuits and Systems Conference, DCAS 2024 - Hybrid, Dallas, United States
Duration: Apr 19 2024 → Apr 21 2024

Publication series

NameProceedings of the 17th IEEE Dallas Circuits and Systems Conference, DCAS 2024

Conference

Conference17th IEEE Dallas Circuits and Systems Conference, DCAS 2024
Country/TerritoryUnited States
CityHybrid, Dallas
Period4/19/24 → 4/21/24

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Modeling and Simulation

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