TY - GEN
T1 - Balancing Speed and Accuracy for Robust Analog-Mixed Signal Circuit Design using Closed-Loop Reinforcement Learning with Ensemble Neural Network Surrogates
AU - Guo, Zuwei
AU - Fu, Jie
AU - Bhanushali, Sumukh
AU - Zeng, Zehua
AU - Banerjee, Imon
AU - Sanyal, Arindam
N1 - Publisher Copyright: © 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - Analog/mixed-signal (AMS) circuit sizing requires exploring high-dimensional, constrained design spaces under expensive SPICE simulations, while maintaining robustness to out-of-distribution (OOD) parameter proposals. We propose a fidelity-aware reinforcement learning framework (RL-PPO-Online) that unifies (i) SPICE-in-the-loop verification and (ii) ensemble neural network guided regularization for surrogate-assisted optimization. Another PPO policy (RL-PPO-Offline) is trained using an ensemble neural network for fast performance prediction, while a discriminator penalizes OOD actions to stabilize surrogate-only updates. We further introduce RL-PPO-Blend, which schedules a small fraction of SPICE queries (0.2-5%) on top of RL-PPO-Offline to provide a tunable speed-fidelity trade-off. On challenging ADC front-end sizing tasks in 28 nm (bootstrapped sampling switch and input buffer + switch), the proposed method improves pass rates over DDPG and LLM baselines, and achieves near-online accuracy with substantially reduced simulation cost.
AB - Analog/mixed-signal (AMS) circuit sizing requires exploring high-dimensional, constrained design spaces under expensive SPICE simulations, while maintaining robustness to out-of-distribution (OOD) parameter proposals. We propose a fidelity-aware reinforcement learning framework (RL-PPO-Online) that unifies (i) SPICE-in-the-loop verification and (ii) ensemble neural network guided regularization for surrogate-assisted optimization. Another PPO policy (RL-PPO-Offline) is trained using an ensemble neural network for fast performance prediction, while a discriminator penalizes OOD actions to stabilize surrogate-only updates. We further introduce RL-PPO-Blend, which schedules a small fraction of SPICE queries (0.2-5%) on top of RL-PPO-Offline to provide a tunable speed-fidelity trade-off. On challenging ADC front-end sizing tasks in 28 nm (bootstrapped sampling switch and input buffer + switch), the proposed method improves pass rates over DDPG and LLM baselines, and achieves near-online accuracy with substantially reduced simulation cost.
KW - Analog-to-Digital Converter (ADC)
KW - Discriminator Regularization
KW - Proximal Policy Optimization (PPO)
KW - Reinforcement Learning
UR - https://www.scopus.com/pages/publications/105043429251
UR - https://www.scopus.com/pages/publications/105043429251#tab=citedBy
U2 - 10.1109/ISCAS66217.2026.11562451
DO - 10.1109/ISCAS66217.2026.11562451
M3 - Conference contribution
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 803
EP - 807
BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Y2 - 24 May 2026 through 27 May 2026
ER -