TY - GEN
T1 - Delta-Sigma Modulator-Based Compute-in-Memory Neural Network with Analog Feature Extraction and Classification for Edge Sensors
AU - Gupta, Tushar
AU - Damodaran, Vasundhara
AU - Liao, Yuan
AU - Seo, Jae-sun
AU - Sanyal, Arindam
N1 - Publisher Copyright: © 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - This work presents an on-chip feature extractor and classifier that reduces sensor transmission by >1000× through on-chip data analysis. The classifier includes reservoir computing (RC) layer for unsupervised feature extraction followed by an artificial neural network (ANN) layer for supervised classification. The RC layer is implemented using switched-capacitor circuits, while the ANN uses a delta-sigma modulator-based 9T1C compute-in-memory (CIM) macro that supports variable-resolution precision. A test chip, fabricated in a 28nm process, is demonstrated for stress and seismic event detection. The test-chip achieves mean classification accuracies of 97.0% for stress detection and 95.8% for seismic event detection, with energy consumption of 1.3nJ/classification for stress and 4.25nJ/classification for seismic events.
AB - This work presents an on-chip feature extractor and classifier that reduces sensor transmission by >1000× through on-chip data analysis. The classifier includes reservoir computing (RC) layer for unsupervised feature extraction followed by an artificial neural network (ANN) layer for supervised classification. The RC layer is implemented using switched-capacitor circuits, while the ANN uses a delta-sigma modulator-based 9T1C compute-in-memory (CIM) macro that supports variable-resolution precision. A test chip, fabricated in a 28nm process, is demonstrated for stress and seismic event detection. The test-chip achieves mean classification accuracies of 97.0% for stress detection and 95.8% for seismic event detection, with energy consumption of 1.3nJ/classification for stress and 4.25nJ/classification for seismic events.
KW - Classifier
KW - Compute-in-Memory
KW - Reservoir Computing
KW - SRAM
KW - Switched Capacitor circuits
UR - https://www.scopus.com/pages/publications/105043446739
UR - https://www.scopus.com/pages/publications/105043446739#tab=citedBy
U2 - 10.1109/ISCAS66217.2026.11562729
DO - 10.1109/ISCAS66217.2026.11562729
M3 - Conference contribution
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 3196
EP - 3200
BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Y2 - 24 May 2026 through 27 May 2026
ER -