Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs

David J. Allstot; San Hwa Chee; Sayfe Kiaei; Manu Shrivastawa

doi:10.1109/81.244904

Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs

David J. Allstot
, San Hwa Chee
, Sayfe Kiaei
, Manu Shrivastawa

Research output: Contribution to journal › Article › peer-review

92 Scopus citations

Abstract

CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔV_L ≌ 0.2F_dd)than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30–300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-rim CMOS process, and simulated results with a standard 1-rim process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 33- and 2.0-V power supplies.

Original language	English (US)
Pages (from-to)	553-563
Number of pages	11
Journal	IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
Volume	40
Issue number	9
DOIs	https://doi.org/10.1109/81.244904
State	Published - Sep 1993
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/81.244904

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title = "Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs",

abstract = "CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔVL ≌ 0.2Fdd)than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30–300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-rim CMOS process, and simulated results with a standard 1-rim process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 33- and 2.0-V power supplies.",

author = "Allstot, \{David J.\} and Chee, \{San Hwa\} and Sayfe Kiaei and Manu Shrivastawa",

note = "Funding Information: Manuscript received December 20, 1991; revised June 22, 1993. This work was supported in part by a grant from the National Science Foundation Center for the Design of Analog-Digital Integrated Circuits (CDADIC) at Washington State University, the University of Washington, and Oregon State University. This paper was recommended by Associate Editor W. M. Dai. D. J. Allstot is with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213. S.-H. Chee is with Linear Technology Corporation, 1630 McCarthy Blvd., Milpitas, CA 95035. S. Kiaei and M. Shrivastawa are with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331. IEEE Log Number 921 1955.",

year = "1993",

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T1 - Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs

AU - Allstot, David J.

AU - Chee, San Hwa

AU - Kiaei, Sayfe

AU - Shrivastawa, Manu

N1 - Funding Information: Manuscript received December 20, 1991; revised June 22, 1993. This work was supported in part by a grant from the National Science Foundation Center for the Design of Analog-Digital Integrated Circuits (CDADIC) at Washington State University, the University of Washington, and Oregon State University. This paper was recommended by Associate Editor W. M. Dai. D. J. Allstot is with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213. S.-H. Chee is with Linear Technology Corporation, 1630 McCarthy Blvd., Milpitas, CA 95035. S. Kiaei and M. Shrivastawa are with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331. IEEE Log Number 921 1955.

PY - 1993/9

Y1 - 1993/9

N2 - CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔVL ≌ 0.2Fdd)than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30–300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-rim CMOS process, and simulated results with a standard 1-rim process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 33- and 2.0-V power supplies.

AB - CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔVL ≌ 0.2Fdd)than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30–300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-rim CMOS process, and simulated results with a standard 1-rim process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 33- and 2.0-V power supplies.

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Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs

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