Hardware-software codesign for dynamically reconfigurable architectures

Ranga Vemuri

doi:10.1007/978-3-540-48302-1_18

Hardware-software codesign for dynamically reconfigurable architectures

Ranga Vemuri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.

Original language	English (US)
Title of host publication	Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings
Editors	Patrick Lysaght, James Irvine, Reiner W. Hartenstein
Publisher	Springer Verlag
Pages	175-185
Number of pages	11
ISBN (Print)	3540664572, 9783540664574
DOIs	https://doi.org/10.1007/978-3-540-48302-1_18
State	Published - 1999
Externally published	Yes
Event	9th International Workshop on Field Programmable Logic and Applications, FPL 1999 - Glasgow, United Kingdom Duration: Aug 30 1999 → Sep 1 1999

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	1673

Other

Other	9th International Workshop on Field Programmable Logic and Applications, FPL 1999
Country/Territory	United Kingdom
City	Glasgow
Period	8/30/99 → 9/1/99

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/978-3-540-48302-1_18

Cite this

Vemuri, R. (1999). Hardware-software codesign for dynamically reconfigurable architectures. In P. Lysaght, J. Irvine, & R. W. Hartenstein (Eds.), Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings (pp. 175-185). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1673). Springer Verlag. https://doi.org/10.1007/978-3-540-48302-1_18

Hardware-software codesign for dynamically reconfigurable architectures. / Vemuri, Ranga.
Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings. ed. / Patrick Lysaght; James Irvine; Reiner W. Hartenstein. Springer Verlag, 1999. p. 175-185 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1673).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Vemuri, R 1999, Hardware-software codesign for dynamically reconfigurable architectures. in P Lysaght, J Irvine & RW Hartenstein (eds), Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 1673, Springer Verlag, pp. 175-185, 9th International Workshop on Field Programmable Logic and Applications, FPL 1999, Glasgow, United Kingdom, 8/30/99. https://doi.org/10.1007/978-3-540-48302-1_18

Vemuri R. Hardware-software codesign for dynamically reconfigurable architectures. In Lysaght P, Irvine J, Hartenstein RW, editors, Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings. Springer Verlag. 1999. p. 175-185. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-48302-1_18

Vemuri, Ranga. / Hardware-software codesign for dynamically reconfigurable architectures. Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings. editor / Patrick Lysaght ; James Irvine ; Reiner W. Hartenstein. Springer Verlag, 1999. pp. 175-185 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{7a84661cedda476ab0abd462efacdd40,

title = "Hardware-software codesign for dynamically reconfigurable architectures",

abstract = "The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.",

author = "Ranga Vemuri",

note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 1999.; 9th International Workshop on Field Programmable Logic and Applications, FPL 1999 ; Conference date: 30-08-1999 Through 01-09-1999",

year = "1999",

doi = "10.1007/978-3-540-48302-1_18",

language = "English (US)",

isbn = "3540664572",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "175--185",

editor = "Patrick Lysaght and James Irvine and Hartenstein, {Reiner W.}",

booktitle = "Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings",

}

TY - GEN

T1 - Hardware-software codesign for dynamically reconfigurable architectures

AU - Vemuri, Ranga

N1 - Publisher Copyright: © Springer-Verlag Berlin Heidelberg 1999.

PY - 1999

Y1 - 1999

N2 - The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.

AB - The paper addresses the problem of mapping an application specified as a task graph on a heterogeneous architecture which contains a software processor, a dynamically reconfigurable hardware coprocessor and memory elements. The problem comprises of three sub-problems: partitioning of tasks between hardware and software, assigning tasks mapped on hardware to different temporal segments and scheduling task execution, reconfiguration of hardware, inter-processor and intra-processor communication. We present a heuristic based technique for solving the problem. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm and experimentation with synthetic graphs.

UR - http://www.scopus.com/inward/record.url?scp=84956862038&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84956862038&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-48302-1_18

DO - 10.1007/978-3-540-48302-1_18

M3 - Conference contribution

SN - 3540664572

SN - 9783540664574

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 175

EP - 185

BT - Field Programmable Logic and Applications - 9th International Workshop, FPL 1999, Proceedings

A2 - Lysaght, Patrick

A2 - Irvine, James

A2 - Hartenstein, Reiner W.

PB - Springer Verlag

T2 - 9th International Workshop on Field Programmable Logic and Applications, FPL 1999

Y2 - 30 August 1999 through 1 September 1999

ER -

Hardware-software codesign for dynamically reconfigurable architectures

Abstract

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