High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing

Jian Gu; Wei Wu; S. Y. Chou

doi:10.1109/DRC.2002.1029501

High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing

Jian Gu, Wei Wu, S. Y. Chou

Basic Medical Sciences, Phoenix

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this work, we report the fabrication of high performance thin-film transistors (TFTs) down to sub-100 nm regime using Pattern-controlled crystallization of Thin channel layer and High temperature annealing (PaTH). High temperature is used to improve the film quality. Thin body thickness (Tsi) is used to suppress the short channel effects. The devices showed superior switching properties and device-to-device uniformity over conventional poly-Si TFTs.

Original language	English (US)
Title of host publication	60th Device Research Conference, DRC 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	49-50
Number of pages	2
ISBN (Electronic)	0780373170
DOIs	https://doi.org/10.1109/DRC.2002.1029501
State	Published - 2002
Event	60th Device Research Conference, DRC 2002 - Santa Barbara, United States Duration: Jun 24 2002 → Jun 26 2002

Publication series

Name	Device Research Conference - Conference Digest, DRC
Volume	2002-January

Other

Other	60th Device Research Conference, DRC 2002
Country/Territory	United States
City	Santa Barbara
Period	6/24/02 → 6/26/02

Keywords

Annealing
Crystallization
Fabrication
Grain boundaries
Immune system
Laboratories
Silicon on insulator technology
Statistics
Temperature
Thin film transistors

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/DRC.2002.1029501

Cite this

Gu, J., Wu, W., & Chou, S. Y. (2002). High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing. In 60th Device Research Conference, DRC 2002 (pp. 49-50). Article 1029501 (Device Research Conference - Conference Digest, DRC; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DRC.2002.1029501

High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing. / Gu, Jian; Wu, Wei; Chou, S. Y.
60th Device Research Conference, DRC 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 49-50 1029501 (Device Research Conference - Conference Digest, DRC; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Gu, J, Wu, W & Chou, SY 2002, High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing. in 60th Device Research Conference, DRC 2002., 1029501, Device Research Conference - Conference Digest, DRC, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 49-50, 60th Device Research Conference, DRC 2002, Santa Barbara, United States, 6/24/02. https://doi.org/10.1109/DRC.2002.1029501

Gu J, Wu W, Chou SY. High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing. In 60th Device Research Conference, DRC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 49-50. 1029501. (Device Research Conference - Conference Digest, DRC). doi: 10.1109/DRC.2002.1029501

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abstract = "In this work, we report the fabrication of high performance thin-film transistors (TFTs) down to sub-100 nm regime using Pattern-controlled crystallization of Thin channel layer and High temperature annealing (PaTH). High temperature is used to improve the film quality. Thin body thickness (Tsi) is used to suppress the short channel effects. The devices showed superior switching properties and device-to-device uniformity over conventional poly-Si TFTs.",

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High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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