Implementation of the Chien search algorithm on a baseband processor

In this paper, we discuss the implementation of the BCH decoder Chien search algorithm on a SIMD style programmable baseband processor with minimum memory footprint and processing time degradation. Due to the emergence of long BCH codes, the computational efficiency of the Chien search algorithm becomes a major implementation issue for BCH decoders. We minimize the memory usage and processing time of the BCH decoders by deriving a computation rule, which is used to efficiently generate the power terms of primitive elements upon the SIMD datapath, instead of storing all pre-computed terms in the memory.