Intrinsic variability and reliability in nano-CMOS

Random variations have been regarded as one of the major barriers of CMOS technology scaling. Besides profound physical effects that result from the vastly increased parameter variations due to manufacturing, performance is also affected with temporal conditions due to reliability degradation. Compact models that physically capture diese effects are crucial to bridge variability and reliability effects with design solutions. By understanding the underlying physics and analyzing the results from atomistic simulations, intrinsic variations from random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF) are presented in mis paper. Temporal parameter shift from aging mechanisms like negative bias temperature instability (NBTI) effect along with their models are also discussed. The statistical interaction of aging effects with static variability is further discussed. Finally, circuit performance variability impacted by random threshold voltage variation is benchmarked.