IP protection for VLSI designs via watermarking of routes

N. Narayan; R. D. Newbould; J. D. Carothers; J. J. Rodriguez; W. T. Holman

IP protection for VLSI designs via watermarking of routes

N. Narayan, R. D. Newbould, J. D. Carothers, J. J. Rodriguez, W. T. Holman

Research output: Contribution to journal › Conference article › peer-review

Abstract

Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

Original language	English (US)
Pages (from-to)	406-410
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
State	Published - 2001
Event	14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States Duration: Sep 12 2001 → Sep 15 2001

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "IP protection for VLSI designs via watermarking of routes",

abstract = "Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.",

author = "N. Narayan and Newbould, {R. D.} and Carothers, {J. D.} and Rodriguez, {J. J.} and Holman, {W. T.}",

year = "2001",

language = "English (US)",

pages = "406--410",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- ; Conference date: 12-09-2001 Through 15-09-2001",

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T1 - IP protection for VLSI designs via watermarking of routes

AU - Narayan, N.

AU - Newbould, R. D.

AU - Carothers, J. D.

AU - Rodriguez, J. J.

AU - Holman, W. T.

PY - 2001

Y1 - 2001

N2 - Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

AB - Intellectual property protection (IPP) has become a major concern in today's CAD and ASIC/SOC industries. This paper presents a watermarking technique for IPP at the physical design level. We propose a method for embedding a watermark by modifying the number of vias or bends used to route the nets in a design. This technique is applicable to digital, analog and mixed-signal design, and has the ability to accommodate the noise tolerance and design intricacies of each.

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M3 - Conference article

SN - 1063-0988

SP - 406

EP - 410

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - 14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World-

Y2 - 12 September 2001 through 15 September 2001

ER -

IP protection for VLSI designs via watermarking of routes

Abstract

ASJC Scopus subject areas

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