Large-scale broad-band parasitic extraction for fast layout verification of 3-D RF and mixed-signal on-chip structures

In this paper, a methodology for efficient parasitic extraction and verification flow for RF and mixed-signal integrated-circuit designs is presented. The implementation of a multiplane precorrected fast Fourier transform (PFFT) computational engine enables the full-wave electromagnetic (EM) simulation of interconnects and passive components. The PFFT algorithm is implemented on a set of two-dimensional fast Fourier transform grids associated with the current sheets corresponding to the conductor loss models. This leads to the full-wave modeling of silicon embedded three-dimensional circuits within the two-and-one-half-dimensional computational framework yielding the O(N log N) computational complexity and O(N) memory requirements of the algorithm. The broad-band capability of the EM solver is provided through the loop-tree/charge implementation of the PFFT algorithm allowing for robust full-wave modeling from dc to microwaves. The EM verification flow is integrated seamlessly within the Cadence environment allowing for non-linear circuit simulation of the entire device. The capability and accuracy of the proposed methodology is demonstrated through EM simulation results for an individual on-chip spiral inductor, as well as a low-noise amplifier.