TY - GEN
T1 - LeakSEAL
T2 - 36th Great Lakes Symposium on VLSI, GLSVLSI 2026
AU - Pugazhenthi, Veeramani
AU - Chowdhury, Md Muhtasim Alam
AU - Ghimire, Sujan
AU - Dharavath, Harish Kumar
AU - Mirfasihi, Parsa
AU - Sehatbakhsh, Nader
AU - Satam, Pratik
AU - Salehi Mobarakeh, Soheil
N1 - Publisher Copyright: © 2026 Copyright held by the owner/author(s).
PY - 2026/6/22
Y1 - 2026/6/22
N2 - On-chip learning enables machine learning models to be trained or updated directly on specialized hardware rather than on external CPUs or GPUs, offering lower latency, improved energy-efficiency, enhanced privacy, and real-time adaptability for edge devices. In Spiking Neural Networks (SNNs), this capability relies on dynamic synaptic weight adaptation, but such adaptability also introduces significant security risks. In this work, we demonstrate a power side-channel attack on a quantized SNN implemented on a CW305 FPGA platform using ChipWhisperer. Our analysis identifies consistent power leakage patterns associated with neuron update operations, allowing an attacker to infer internal model attributes without direct access to the model's weights or inputs. We further perform Correlation Power Analysis (CPA) with a Hamming Weight leakage model to recover secret synaptic weights with high confidence using as few as 1,500 power traces. These results expose critical vulnerabilities in on-chip learning systems and SNN architectures, highlight realistic threats to IoT and edge applications, and motivate mitigation strategies at the software-hardware boundary, including secure design practices, cryptographic protections, and access control mechanisms, without significantly degrading performance.
AB - On-chip learning enables machine learning models to be trained or updated directly on specialized hardware rather than on external CPUs or GPUs, offering lower latency, improved energy-efficiency, enhanced privacy, and real-time adaptability for edge devices. In Spiking Neural Networks (SNNs), this capability relies on dynamic synaptic weight adaptation, but such adaptability also introduces significant security risks. In this work, we demonstrate a power side-channel attack on a quantized SNN implemented on a CW305 FPGA platform using ChipWhisperer. Our analysis identifies consistent power leakage patterns associated with neuron update operations, allowing an attacker to infer internal model attributes without direct access to the model's weights or inputs. We further perform Correlation Power Analysis (CPA) with a Hamming Weight leakage model to recover secret synaptic weights with high confidence using as few as 1,500 power traces. These results expose critical vulnerabilities in on-chip learning systems and SNN architectures, highlight realistic threats to IoT and edge applications, and motivate mitigation strategies at the software-hardware boundary, including secure design practices, cryptographic protections, and access control mechanisms, without significantly degrading performance.
KW - Correlation Power Analysis
KW - Edge AI
KW - FPGA Security
KW - On-Chip Learning.
KW - Power Side-Channel Analysis
KW - Spiking Neural Networks
UR - https://www.scopus.com/pages/publications/105045021555
UR - https://www.scopus.com/pages/publications/105045021555#tab=citedBy
U2 - 10.1145/3787109.3816388
DO - 10.1145/3787109.3816388
M3 - Conference contribution
T3 - GLSVLSI 2026 - Proceedings of the Great Lakes Symposium on VLSI 2026
SP - 135
EP - 140
BT - GLSVLSI 2026 - Proceedings of the Great Lakes Symposium on VLSI 2026
A2 - Chen, Fan
A2 - Zhou, Peipei
A2 - Gu, Jie
A2 - Trivedi, Amit R.
A2 - Yang, Xiaoxuan
PB - Association for Computing Machinery, Inc
Y2 - 22 June 2026 through 24 June 2026
ER -