Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers

Sumit Bhardwaj; Soroush Moallemi; Jennifer Kitchen

doi:10.1109/DCAS51144.2020.9330649

Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers

Sumit Bhardwaj, Soroush Moallemi, Jennifer Kitchen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

This work discusses about the linearity challenges of a radio frequency power amplifier (RF-PA) using envelope tracking (ET) technique. ET modulators vary the supply voltage of a PA to improve its efficiency, but also add undesired ripple at the supply node which affect the PA's linearity. Also, device non-linearities of the PA add distortion to the transmitted signal and degrade its spectral purity. To overcome the aforementioned issues, a fully differential common-drain architecture for the PA is proposed and linearity enhancement is demonstrated in TSMC CMOS 65 nm technology.

Original language	English (US)
Title of host publication	Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728185101
DOIs	https://doi.org/10.1109/DCAS51144.2020.9330649
State	Published - Nov 15 2020
Event	14th IEEE Dallas Circuits and Systems Conference, DCAS 2020 - Virtual, Richardson, United States Duration: Nov 15 2020 → Nov 16 2020

Publication series

Name	Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020

Conference

Conference	14th IEEE Dallas Circuits and Systems Conference, DCAS 2020
Country/Territory	United States
City	Virtual, Richardson
Period	11/15/20 → 11/16/20

Keywords

Envelope tracking
Inter-modulation distortion
Linearity enhancement
Power amplifier

ASJC Scopus subject areas

Artificial Intelligence
Hardware and Architecture
Signal Processing
Energy Engineering and Power Technology
Electrical and Electronic Engineering

Access to Document

10.1109/DCAS51144.2020.9330649

Cite this

Bhardwaj, S., Moallemi, S., & Kitchen, J. (2020). Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers. In Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020 Article 9330649 (Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DCAS51144.2020.9330649

Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers. / Bhardwaj, Sumit; Moallemi, Soroush; Kitchen, Jennifer.
Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9330649 (Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bhardwaj, S, Moallemi, S & Kitchen, J 2020, Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers. in Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020., 9330649, Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020, Institute of Electrical and Electronics Engineers Inc., 14th IEEE Dallas Circuits and Systems Conference, DCAS 2020, Virtual, Richardson, United States, 11/15/20. https://doi.org/10.1109/DCAS51144.2020.9330649

Bhardwaj S, Moallemi S, Kitchen J. Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers. In Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9330649. (Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020). doi: 10.1109/DCAS51144.2020.9330649

Bhardwaj, Sumit ; Moallemi, Soroush ; Kitchen, Jennifer. / Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers. Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. (Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference, DCAS 2020).

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title = "Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers",

abstract = "This work discusses about the linearity challenges of a radio frequency power amplifier (RF-PA) using envelope tracking (ET) technique. ET modulators vary the supply voltage of a PA to improve its efficiency, but also add undesired ripple at the supply node which affect the PA's linearity. Also, device non-linearities of the PA add distortion to the transmitted signal and degrade its spectral purity. To overcome the aforementioned issues, a fully differential common-drain architecture for the PA is proposed and linearity enhancement is demonstrated in TSMC CMOS 65 nm technology. ",

keywords = "Envelope tracking, Inter-modulation distortion, Linearity enhancement, Power amplifier",

author = "Sumit Bhardwaj and Soroush Moallemi and Jennifer Kitchen",

note = "Funding Information: ACKNOWLEDGMENT This research was funded by the NSF I/UCRC Center for Embedded Systems. Publisher Copyright: {\textcopyright} 2020 IEEE.; 14th IEEE Dallas Circuits and Systems Conference, DCAS 2020 ; Conference date: 15-11-2020 Through 16-11-2020",

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N2 - This work discusses about the linearity challenges of a radio frequency power amplifier (RF-PA) using envelope tracking (ET) technique. ET modulators vary the supply voltage of a PA to improve its efficiency, but also add undesired ripple at the supply node which affect the PA's linearity. Also, device non-linearities of the PA add distortion to the transmitted signal and degrade its spectral purity. To overcome the aforementioned issues, a fully differential common-drain architecture for the PA is proposed and linearity enhancement is demonstrated in TSMC CMOS 65 nm technology.

AB - This work discusses about the linearity challenges of a radio frequency power amplifier (RF-PA) using envelope tracking (ET) technique. ET modulators vary the supply voltage of a PA to improve its efficiency, but also add undesired ripple at the supply node which affect the PA's linearity. Also, device non-linearities of the PA add distortion to the transmitted signal and degrade its spectral purity. To overcome the aforementioned issues, a fully differential common-drain architecture for the PA is proposed and linearity enhancement is demonstrated in TSMC CMOS 65 nm technology.

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Linearity enhancement using a common-drain topology for envelope tracking CMOS power amplifiers

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this