Low-impedance load detector circuit for optical interconnects

Optical interconnects provide an alternative for long-distance electrical clock distribution in high-speed VLSI circuits. In an optical interconnect system, the response of the detector circuit is an important factor in determining the speed of the overall system. A simple, low-impedance nMOS detector circuit is presented and modeled for optical interconnect application in CMOS systems. A maximum-current parameter is defined and optimized to improve the circuit response. For 0.5-mW optical input power and a 25-μm-diameter detector, response times of 2.2, 1.1, and 0.8 ns can be achieved with typical 2.0-, 1.0-, and 0.5-μm technologies. With higher optical power or a smaller detector diameter, the response is faster. Analytical results, SPICE simulations, and preliminary experimental results are illustrated and discussed.