Methods for designing low-leakage ESD power supply clamps

Timothy J. Maloney; Steven S. Poon

doi:10.1016/j.elstat.2004.03.005

Methods for designing low-leakage ESD power supply clamps

Timothy J. Maloney, Steven S. Poon

Arizona State University

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

Original language	English (US)
Pages (from-to)	85-97
Number of pages	13
Journal	Journal of Electrostatics
Volume	62
Issue number	2-3 SPEC. ISS.
DOIs	https://doi.org/10.1016/j.elstat.2004.03.005
State	Published - Oct 1 2004

Keywords

Back gate bias
ESD protection
Electrostatic discharge
IC design for reliability
Low leakage
MOSFET
PMOS
Power clamp
RC trigger

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Biotechnology
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.elstat.2004.03.005

Cite this

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title = "Methods for designing low-leakage ESD power supply clamps",

abstract = "Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.",

keywords = "Back gate bias, ESD protection, Electrostatic discharge, IC design for reliability, Low leakage, MOSFET, PMOS, Power clamp, RC trigger",

author = "Maloney, {Timothy J.} and Poon, {Steven S.}",

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AU - Poon, Steven S.

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N2 - Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

AB - Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

KW - Back gate bias

KW - ESD protection

KW - Electrostatic discharge

KW - IC design for reliability

KW - Low leakage

KW - MOSFET

KW - PMOS

KW - Power clamp

KW - RC trigger

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JO - Journal of Electrostatics

JF - Journal of Electrostatics

IS - 2-3 SPEC. ISS.

ER -

Methods for designing low-leakage ESD power supply clamps

Abstract

Keywords

ASJC Scopus subject areas

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