Abstract
Low power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.
Original language | English (US) |
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Title of host publication | Electrical Overstress/Electrostatic Discharge Symposium Proceedings |
Publisher | ESD Association |
Volume | 2003-January |
ISBN (Print) | 1585370576, 9781585370573 |
State | Published - 2003 |
Externally published | Yes |
Event | 25th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2003 - Las Vegas, United States Duration: Sep 21 2003 → Sep 25 2003 |
Other
Other | 25th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2003 |
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Country/Territory | United States |
City | Las Vegas |
Period | 9/21/03 → 9/25/03 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering