TY - GEN
T1 - Novel 8-inch wafer scale process for low-cost production of back side illuminated (BSI) imaging sensors
AU - Joshi, Atul
AU - Chiaverini, David J.
AU - Kashyap, Sachin
AU - Madhugiri, Vishwanath
AU - Patti, Robert
AU - Hong, Sangki
AU - Lesser, Michael
N1 - Publisher Copyright: © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.
PY - 2021
Y1 - 2021
N2 - An 8-inch wafer scale process was developed that provides low cost availability of back-side illuminated (BSI) imaging sensors. The process has been optimized to convert standard CMOS and CCD 6-inch or 8-inch wafers from front side illuminated (FSI) sensors to BSI sensors. The process successfully demonstrates wafer planarization, bow correction, bonding to carrier wafers, wafer thinning, re-planarization, anti-reflection coating, through silicon vias (TSVs) and back side metallization. Good wafer thinning control was obtained for a wide range of epi thicknesses varying from 4 microns to 15 microns. The thinner epi is optimized for UV and visible sensing while the thicker epi material is optimized for near-infrared (NIR) sensing. The processed wafers demonstrate backside passivation and anti-reflection (AR) coatings that optimize the QE performance in a variety of bands such as 200nm-300nm, 300nm-400nm and 400nm-900nm.
AB - An 8-inch wafer scale process was developed that provides low cost availability of back-side illuminated (BSI) imaging sensors. The process has been optimized to convert standard CMOS and CCD 6-inch or 8-inch wafers from front side illuminated (FSI) sensors to BSI sensors. The process successfully demonstrates wafer planarization, bow correction, bonding to carrier wafers, wafer thinning, re-planarization, anti-reflection coating, through silicon vias (TSVs) and back side metallization. Good wafer thinning control was obtained for a wide range of epi thicknesses varying from 4 microns to 15 microns. The thinner epi is optimized for UV and visible sensing while the thicker epi material is optimized for near-infrared (NIR) sensing. The processed wafers demonstrate backside passivation and anti-reflection (AR) coatings that optimize the QE performance in a variety of bands such as 200nm-300nm, 300nm-400nm and 400nm-900nm.
KW - Back side illumination (BSI)
KW - CCD image sensor
KW - CMOS image sensor (CIS)
KW - Front side illumination (FSI)
KW - NIR
KW - Planarization
KW - Silicon wafer process
KW - UV
KW - Wafer bonding
KW - Wafer thinning
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U2 - 10.1117/12.2588181
DO - 10.1117/12.2588181
M3 - Conference contribution
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Image Sensing Technologies
A2 - Dhar, Nibir K.
A2 - Dutta, Achyut K.
A2 - Babu, Sachidananda R.
PB - SPIE
T2 - Image Sensing Technologies: Materials, Devices, Systems, and Applications VIII 2021
Y2 - 12 April 2021 through 16 April 2021
ER -