Parasitic-aware synthesis of RF CMOS switching power amplifiers

Kiyong Choi; David J. Allstot; Sayfe Kiaei

Parasitic-aware synthesis of RF CMOS switching power amplifiers

Kiyong Choi
, David J. Allstot
, Sayfe Kiaei

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
State	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002

Other

Other	2002 IEEE International Symposium on Circuits and Systems
Country/Territory	United States
City	Phoenix, AZ
Period	5/26/02 → 5/29/02

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

@inproceedings{96665367bd2f41e49d9ea1bd56836d71,

title = "Parasitic-aware synthesis of RF CMOS switching power amplifiers",

abstract = "Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49\% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.",

author = "Kiyong Choi and Allstot, \{David J.\} and Sayfe Kiaei",

year = "2002",

language = "English (US)",

volume = "1",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

}

TY - GEN

T1 - Parasitic-aware synthesis of RF CMOS switching power amplifiers

AU - Choi, Kiyong

AU - Allstot, David J.

AU - Kiaei, Sayfe

PY - 2002

Y1 - 2002

N2 - Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.

AB - Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.

UR - https://www.scopus.com/pages/publications/0036280890

UR - https://www.scopus.com/pages/publications/0036280890#tab=citedBy

M3 - Conference contribution

VL - 1

BT - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

Parasitic-aware synthesis of RF CMOS switching power amplifiers

Abstract

Other

ASJC Scopus subject areas

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