TY - GEN
T1 - Path-based test composition for mixed-signal SOC's
AU - Ozev, S.
AU - Orailoglu, A.
N1 - Funding Information: This work is supported through a grant by National Semiconductor, Inc., Agilent Technologies, and the UC Micro Office. Publisher Copyright: © 2000 IEEE.
PY - 2000
Y1 - 2000
N2 - We outline a methodology for system level test composition out of module level tests in the context of system-on-a-chip (SOC). The method can be utilized as soon as high level specifications are available providing avenues for testability insertion. The digital/analog interface is handled by a conversion from digital bits to analog signals. Experimental results show that high fault and yield coverages for most tests can be attained with no hardware alterations.
AB - We outline a methodology for system level test composition out of module level tests in the context of system-on-a-chip (SOC). The method can be utilized as soon as high level specifications are available providing avenues for testability insertion. The digital/analog interface is handled by a conversion from digital bits to analog signals. Experimental results show that high fault and yield coverages for most tests can be attained with no hardware alterations.
UR - https://www.scopus.com/pages/publications/84961997680
UR - https://www.scopus.com/pages/publications/84961997680#tab=citedBy
U2 - 10.1109/SSMSD.2000.836464
DO - 10.1109/SSMSD.2000.836464
M3 - Conference contribution
T3 - 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000
SP - 153
EP - 158
BT - 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Southwest Symposium on Mixed-Signal Design, SSMSD 2000
Y2 - 27 February 2000 through 29 February 2000
ER -