Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores

Dan Zhao; Unni Chandran; Hideo Fujiwara

doi:10.1109/ASPDAC.2007.358071

Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores

Dan Zhao
, Unni Chandran
, Hideo Fujiwara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.

Original language	English (US)
Title of host publication	Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages	714-719
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2007.358071
State	Published - 2007
Externally published	Yes
Event	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan Duration: Jan 23 2007 → Jan 27 2007

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Country/Territory	Japan
City	Yokohama
Period	1/23/07 → 1/27/07

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2007.358071

Cite this

Zhao, D., Chandran, U., & Fujiwara, H. (2007). Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 714-719). Article 4196117 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.358071

Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores. / Zhao, Dan; Chandran, Unni; Fujiwara, Hideo.
Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 714-719 4196117 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhao, D, Chandran, U & Fujiwara, H 2007, Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196117, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 714-719, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 1/23/07. https://doi.org/10.1109/ASPDAC.2007.358071

Zhao D, Chandran U, Fujiwara H. Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 714-719. 4196117. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2007.358071

@inproceedings{dd25219e793f4b5abd92a820d337705c,

title = "Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores",

abstract = "This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.",

author = "Dan Zhao and Unni Chandran and Hideo Fujiwara",

year = "2007",

doi = "10.1109/ASPDAC.2007.358071",

language = "English (US)",

isbn = "1424406293",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "714--719",

booktitle = "Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007",

note = "ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 ; Conference date: 23-01-2007 Through 27-01-2007",

}

TY - GEN

T1 - Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores

AU - Zhao, Dan

AU - Chandran, Unni

AU - Fujiwara, Hideo

PY - 2007

Y1 - 2007

N2 - This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.

AB - This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.

UR - https://www.scopus.com/pages/publications/34548824145

UR - https://www.scopus.com/pages/publications/34548824145#tab=citedBy

U2 - 10.1109/ASPDAC.2007.358071

DO - 10.1109/ASPDAC.2007.358071

M3 - Conference contribution

SN - 1424406293

SN - 9781424406296

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 714

EP - 719

BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

Y2 - 23 January 2007 through 27 January 2007

ER -

Shelf packing to the design and optimization of a power-aware multi-frequency wrapper architecture for modular IP cores

Abstract

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Other

ASJC Scopus subject areas

Access to Document

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