Stochastic ΔΣ VCO-ADC Utilizing 4x Staggered Averaging

Sanjeev Tannirkulam Chandrasekaran; Arindam Sanyal

doi:10.1109/ISCAS45731.2020.9180835

Stochastic ΔΣ VCO-ADC Utilizing 4x Staggered Averaging

Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.

Original language	English (US)
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-January
DOIs	https://doi.org/10.1109/ISCAS45731.2020.9180835
State	Published - 2020
Externally published	Yes
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: Oct 10 2020 → Oct 21 2020

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS45731.2020.9180835

Cite this

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title = "Stochastic ΔΣ VCO-ADC Utilizing 4x Staggered Averaging",

abstract = "This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.",

author = "Chandrasekaran, {Sanjeev Tannirkulam} and Arindam Sanyal",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

doi = "10.1109/ISCAS45731.2020.9180835",

language = "English (US)",

volume = "2020-January",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - Stochastic ΔΣ VCO-ADC Utilizing 4x Staggered Averaging

AU - Chandrasekaran, Sanjeev Tannirkulam

AU - Sanyal, Arindam

PY - 2020

Y1 - 2020

N2 - This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.

AB - This work presents a stochastic ring voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.

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DO - 10.1109/ISCAS45731.2020.9180835

M3 - Conference article

SN - 0271-4310

VL - 2020-January

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

Stochastic ΔΣ VCO-ADC Utilizing 4x Staggered Averaging

Abstract

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